TSMC and Synopsys Collaboration Delivers Design Flow for TSMCs WoW and CoWoS Packaging Technologies
Highlights:
Synopsys Design Platform enabled for TSMC's WoW direct stacking and CoWoS technologies
Solution includes multi-die and interposer layout implementation as well as parasitic extraction and timing analysis coupled with physical verification
Reference flow enables early customers to realize the full potential of 3D-IC for high-performance and low-power applications
"High-performance advanced 3D silicon fabrication and wafer stacking technologies require new EDA features and flows to support the corresponding increase in design and verification complexity," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "We extend our collaboration with Synopsys to deliver design solutions for TSMC's CoWoS and WoW advanced packaging technologies. We look forward to our mutual customers benefiting from the enabled design solutions, boosting designer productivity and accelerating time-to-market."
"Built through deep collaboration, the design solution and reference flow for TSMC's WoW and CoWoS chip integration solutions will enable our mutual customers to achieve optimal quality of results," said Michael Jackson, corporate vice president of marketing and business development for Synopsys' Design Group. "The Synopsys Design Platform and methodologies will allow designers to confidently meet their schedules for cost-effective, high-performance, and low-power multi-die solutions."
Synopsys Design Platform Enabled for TSMC's Multi-die 3D-IC Advanced Packaging Technologies
